Fresher 2012
Posted on: 2012-09-27
Curriculum Vitae
R.K.L.Saraswathi Devi,
D/O R.K.Lokanathan,
4-103,Balaji Nagar,
Greamspet (post),
Chittoor-517002. Email Id: (email hidden)
Andhra Pradesh. Mobile number: 00(phone hidden)18
Objective
To work in a fast growing field and in an organization which will give me job satisfaction and make me strong in my field of interest.
Academic credentials
Degree/Board/ Examination | Specialization | University/ College/School | Marks in percentage | Year |
M.Tech | VLSI System Design | J.N.T.U, Ananthapur. | 67% | 2012 |
B.Tech | Electronics and Communications Engineering | J.N.T.U, Hyderabad | 59% | 2009 |
Board of Intermediate education | M.P.C | P.C.R.Govt Junior college, Chittoor | 65% | 2005 |
School of Secondary Education | S.S.C | M.H.School, Chittoor, Andhra Pradesh | 80.5% | 2003 |
Achievements
- Essay writing district level first prize.
- Prizes in quiz competitions.
- School people leader in school.
- Participant in district science center exhibition.
- Drawing competition first prize town level.
- Elocution first prize.
- Always stood within first three positions of school.
Technical skills
Programming languages: C, C++, VHDL, Verilog HDL, SystemVerilog,
PERL scripting, VB scripting, HTML, JAVA script.
Simulators: Tanner EDA tool, Modelsim,Keil microvision 2, MATLAB.
Operating Systems: Windows XP, Linux.
Synthesis tools: Xilinx ISE, Altera quartusII.
Hardware testing tools: Multimeter, oscilloscope.
Area’s of interest
FPGA architecture and applications, Digital Integrated circuit design, ASIC design,
VLSI technology, real-time operating systems.
Academic Project Details
M.Tech project
Title | Design and characterization of parallel prefix adders using FPGA’s |
period | November 2011-September 2012 |
client | Sreenivasa Institute of Technology and Management Studies, JNTU-A, Chittoor. |
The project | Parallel-prefix adders (also known as carry tree adders) give the best performance in VLSI designs. This project investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares them to the simple Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). These designs of varied bit-widths were implemented on a Xilinx Spartan 3E FPGA and delay measurements were made. Due to the presence of a fast carry-chain, the RCA designs exhibit better delay performance up to 128 bits. The carry-tree adders are expected to have a speed advantage over the RCA as bit widths approach 256. |
Role/Responsibilities
| Designed parallel prefix adders and RCA and carry skip adder. These designs of varied bit width were implemented on xilinx Spartan 3E and Spartan 6 FPGAS and delay, area, power measurements were made. The RCA gave better delay, area, power performance up to 128 bits. The carry tree adders are given speed advantage over the RCA as bit width approach 256. |
Languages used | VHDL |
Hardware /tools | Xilinx ISE 13.3 Version, Modelsim. |
B.Tech project
Title | Passenger information system using GSM |
Period | January 2009 - February 2009 |
Client | Integral Coach Factory, Electrical Department, Govt of India, Chennai. |
The project | This project describes challenges of urban transportation and one of the cost effective approach to intelligently manage the public transpiration in the city. In this world passengers used to travel by trains for their comfort .For a new person, its not comfort to find destination. To avoid this problem, we sent an information to passenger trough GSM & GPS. If the destination is tracked by GPS & GSM technology an indication is provided for passenger. User can make awake by himself through these system ,with the help of SMS alert to the passengers whose mobile number is saved at the memory through GSM |
Role/responsible | Team member |
Languages used | C Language |
Hardware/tools | Microcontroller, Kiel Compiler. |
Title | Implementation of 128–bit Satellite Frame Synchronization using VHDL |
Client | National Remote Sensing Agency, Department of Space, Govt of India, Hyderabad. |
Period | May 2008 - June 2008 |
The project | The satellite data comes in the form of frames. It has fixed size and fixed FSC. Each frame consists of FSC and video data. The data from a particular satellite can be accessed only if its FSC is known. To detect and FSC and do further processing, standard frame synchronization units are employed. |
Role/responsible | Team member |
Languages used | VHDL |
Hardware/tools | Altera Quartus II software |
Hobbies
Reading books, drawing, dancing, driving, swimming, playing chess.
Personal details
v Name : R.K.L.Saraswathi Devi
v Date of birth : 20-06-1988
v Sex : Female
v Languages known: English, Telugu, Hindi, Tamil.
Declaration
I here by declare that the above mentioned information is correct and I bear the responsibility for the correctness of the above mentioned particulars.
(R.K.L.Saraswathi Devi)